As a substitute for the IEEE 754-2008 floating-point standard, Posit, a new kind of number\nsystem for floating-point numbers, was put forward recently. Hitherto, some studies have proven\nthat Posit is a better floating-point style than IEEE 754-2008 in some fields. However, most of these\nstudies presented the advantages of Posit from the arithmetical aspect, but none of them suggested\nit had a better hardware implementation than that of IEEE 754-2008. In this paper, we propose\nseveral hardware implementations that contain the Posit adder/subtractor, multiplier, divider, and\nsquare root. Our goal is to achieve an arbitrary Posit format and exploit the minimum circuit\narea, which is required in embedded devices. To implement the minimum circuit area for the\ndivider and square root, the alternating addition and subtraction method is used rather than the\nNewtonâ??Raphson method. Compared with other works, the area of our divider is about 0.2Ã?â??0.7Ã?\n(FPGA). Furthermore, this paper provides the synthesis results for each critical module with the\nXilinx Virtex-7 FPGA VC709 platform.
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